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BD6088GUL
Address 1Dh
< OUT KEY Output Mode setting >
Technical Note
Address
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1Dh
W
FPWM
-
-
-
KBSLP (1) KBSLP (0) OUTSLP(1) OUTSLP(0)
Initial
Value
00h
0
-
-
-
0
0
0
0
Bit7 :
FPWM
Key Driver, OUT1 ～ 4 PWM cycle setting
“0” : 2.048 ms
“1” : 4.096 ms
Refer to “(13) Key back light PWM control” of “The explanation of ALC” and
“The explanation of OUTPWM control” for detail.
Bit [6:4] : ( 未使用 )
Bit [3:2] : KBSLP(1:0) The slope time of around 1step for Key Driver PWM
FPWM=0 FPWM=1
“00” : 0.00 ms 0.00 ms
“01” : 16.38 ms 32.77 ms
“10” : 32.77 ms 65.54 ms
“11” : 65.54 ms 131.08 ms
Refer to “(13) Key back light PWM control” of “The explanation of ALC” for detail.
Bit [1:0] : OUTSLP(1:0)
The slope time of around 1step for OUT1 ～ 4 PWM
FPWM=0 FPWM=1
“00” : 0.00 ms 0.00 ms
“01” : 16.38 ms 32.77 ms
“10” : 32.77 ms 65.54 ms
“11” : 65.54 ms 131.08 ms
Refer to “The explanation of OUTPWM control” for detail.
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28/51
2011.04 - Rev.A
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